Application of Wireless Sensor and Actuator Networks to Achieve Intelligent Microgrids: A Promising Approach towards a Global Smart Grid Deployment

Smart Grids (SGs) constitute the evolution of the traditional electrical grid towards a new paradigm, which should increase the reliability, the security and, at the same time, reduce the costs of energy generation, distribution and consumption. Electrical microgrids (MGs) can be considered the first stage of this evolution of the grid, because of the intelligent management techniques that must be applied to assure their correct operation. To accomplish this task, sensors and actuators will be necessary, along with wireless communication technologies to transmit the measured data and the command messages. Wireless Sensor and Actuator Networks (WSANs) are therefore a promising solution to achieve an intelligent management of MGs and, by extension, the SG. In this frame, this paper surveys several aspects concerning the application of WSANs to manage MGs and the electrical grid, as well as the communication protocols that could be applied. The main concerns regarding the SG deployment are also presented, including future scenarios where the interoperability of different generation technologies must be assured

Introducing the Electronic Knowledge Framework into the Traditional Automotive Suppliers’ Industry: From Mechanical Engineering to Mechatronics

The automotive sector is undergoing radical changes. New trends such as electrification, autonomous driving, connectivity, and car-sharing—to name a few—are disturbing the carmakers, which must satisfy their clients while meeting the increasingly strict environmental regulations. This pressure also falls on automotive parts suppliers, which now are asked to manufacture high-added-value integral systems, while struggling to keep a very adjusted price. As traditional automotive components evolve into electronic systems, suppliers must gain digital mastery to remain competitive. This paper presents different ways of introducing e-skills in a company and illustrates this with some examples from the Basque automotive industry. The aim is to encourage corporations to take the step towards digitalization, providing different options for them to choose the one that best suits their current scenario. For this study we have analyzed the literature and the press releases of the component manufacturers and interviewed staff from some of them. This research seeks to provide solutions so that the automotive sector remains competitive, as it is a strategic sector for the economy and employment.This work has been partially supported by the grant ‘Ayudas para el desarrollo de proyectos de I+D mediante la contratación de personas doctoradas y la realización de doctorados industriales, programa BIKAINTEK 2019’, by the Department of Economic Development, Sustainability and Environment of the Basque Government. Additionally, this work has been partially supported by Eusko Jaularitza-Gobierno Vasco (HAZITEK ESTRATEGICOS 2020 ZL-2020/00022-PILAR-y 2021 ZL-2021/00931-COMMUTE-), by CDTI (IDI-20201264) and FEDER funds

High performance platform to detect faults in the Smart Grid by Artificial Intelligence inference

Inferring faults throughout the power grid involves fast calculation, large scale of data, and low latency. Our heterogeneous architecture in the edge offers such high computing performance and throughput using an Artificial Intelligence (AI) core deployed in the Alveo accelerator. In addition, we have described the process of porting standard AI models to Vitis AI and discussed its limitations and possible implications. During validation, we designed and trained some AI models for fast fault detection in Smart Grids. However, the AI framework is standard, and adapting the models to Field Programmable Gate Arrays (FPGA) has demanded a series of transformation processes. Compared with the Graphics Processing Unit platform, our implementation on the FPGA accelerator consumes less energy and achieves lower latency. Finally, our system balances inference accuracy, on-chip resources consumed, computing performance, and throughput. Even with grid data sampling rates as high as 800,000 per second, our hardware architecture can simultaneously process up to 7 data streams.10.13039/501100000780-European Commission (Grant Number: FEDER) 10.13039/501100003086-Eusko Jaurlaritza (Grant Number: ZE-2020/00022 and ZE-2021/00931) 10.13039/100015866-Hezkuntza, Hizkuntza Politika Eta Kultura Saila, Eusko Jaurlaritza (Grant Number: IT1440-22) 10.13039/501100004837-Ministerio de Ciencia e Innovación (Grant Number: IDI-20201264 and IDI-20220543

Specific Electronic Platform to Test the Influence of Hypervisors on the Performance of Embedded Systems

[EN] Some complex digital circuits must host various operating systems in a single electronic platform to make real-time and not-real-time tasks compatible or assign different priorities to current applications. For this purpose, some hardware–software techniques—called virtualization—must be integrated to run the operating systems independently, as isolated in different processors: virtual machines. These are monitored and managed by a software tool named hypervisor, which is in charge of allowing each operating system to take control of the hardware resources. Therefore, the hypervisor determines the effectiveness of the system when reacting to events. To measure, estimate or compare the performance of different ways to configure the virtualization, our research team has designed and implemented a specific testbench: an electronic system, based on a complex System on Chip with a processing system and programmable logic, to configure the hardware–software partition and show merit figures, to evaluate the performance of the different options, a field that has received insufficient attention so far. In this way, the fabric of the Field Programmable Gate Array (FPGA) can be exploited for measurements and instrumentation. The platform has been validated with two hypervisors, Xen and Jailhouse, in a multiprocessor System-on-Chip, by executing real-time operating systems and application programs in different contexts.This work has been supported by the Basque Government within the project HAZITEK ZE-2020/00022 as well as the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20201264 and FEDER fund

Time Sensitive Networking Protocol Implementation for Linux End Equipment

By bringing industrial-grade robustness and reliability to Ethernet, Time Sensitive Networking (TSN) offers an IEEE standard communication technology that enables interoperability between standard-conformant industrial devices from any vendor. It also eliminates the need for physical separation of critical and non-critical communication networks, which allows a direct exchange of data between operation centers and companies, a concept at the heart of the Industrial Internet of Things (IIoT). This article describes creating an end-to-end TSN network using specialized PCI Express (PCIe) cards and two final Linux endpoints. For this purpose, the two primary standards of TSN, IEEE 802.1AS (regarding clock synchronization), and IEEE 802.1Qbv (regarding time scheduled traffic) have been implemented in Linux equipment as well as a configuration and monitoring system.This work has been supported by the Ministerio de Economía y Competitividad of Spain within the project TEC2017-84011-R and FEDER funds as well as by the Department of Education of the Basque Government within the fund for research groups of the Basque university system IT978-16

Next-Generation Pedal: Integration of Sensors in a Braking Pedal for a Full Brake-by-Wire System

This article presents a novel approach to designing and validating a fully electronic braking pedal, addressing the growing integration of electronics in vehicles. With the imminent rise of brake-by-wire (BBW) technology, the brake pedal requires electronification to keep pace with industry advancements. This research explores technologies and features for the next-generation pedal, including low-power consumption electronics, cost-effective sensors, active adjustable pedals, and a retractable pedal for autonomous vehicles. Furthermore, this research brings the benefits of the water injection technique (WIT) as the base for manufacturing plastic pedal brakes towards reducing cost and weight while enhancing torsional stiffness. Communication with original equipment manufacturers (OEMs) has provided valuable insights and feedback, facilitating a productive exchange of ideas. The findings include two sensor prototypes utilizing inductive technology and printed-ink gauges. Significantly, reduced power consumption was achieved in a Hall-effect sensor already in production. Additionally, a functional BBW prototype was developed and validated. This research presents an innovative approach to pedal design that aligns with current electrification trends and autonomous vehicles. It positions the braking pedal as an advanced component that has the potential to redefine industry standards. In summary, this research significantly contributes to the electronic braking pedal technology presenting the critical industry needs that have driven technical studies and progress in the field of sensors, electronics, and materials, highlighting the challenges that component manufacturers will inevitably face in the forthcoming years.This work has been partially supported by the grant “Ayudas para el desarrollo de proyectos de I+D mediante la contratación de personas doctoradas y la realización de doctorados industriales, programa BIKAINTEK 2019” by the Department of Economic Development, Sustainability, and Environment of the Basque Government. Additionally, this work has been partially supported by the Government of Spain, through the Center for the Development of Industrial Technology (CDTI) under grant agreement IDI-20200198 and by Eusko Jaularitza-Gobierno Vasco (SOC4CRIS KK-2023/00015)

Evaluating Latency in Multiprocessing Embedded Systems for the Smart Grid

Smart grid endpoints need to use two environments within a processing system (PS), one with a Linux-type operating system (OS) using the Arm Cortex-A53 cores for management tasks, and the other with a standalone execution or a real-time OS using the Arm Cortex-R5 cores. The Xen hypervisor and the OpenAMP framework allow this, but they may introduce a delay in the system, and some messages in the smart grid need a latency lower than 3 ms. In this paper, the Linux thread latencies are characterized by the Cyclictest tool. It is shown that when Xen hypervisor is used, this scenario is not suitable for the smart grid as it does not meet the 3 ms timing constraint. Then, standalone execution as the real-time part is evaluated, measuring the delay to handle an interrupt created in programmable logic (PL). The standalone application was run in A53 and R5 cores, with Xen hypervisor and OpenAMP framework. These scenarios all met the 3 ms constraint. The main contribution of the present work is the detailed characterization of each real-time execution, in order to facilitate selecting the most suitable one for each application.This work has been supported by the Ministerio de Economía y Competitividad of Spain within the project TEC2017-84011-R and FEDER funds as well as by the Department of Education of the Basque Government within the fund for research groups of the Basque university system IT978-16. It has also been supported by the Basque Government within the project HAZITEK ZE-2020/00022 as well as the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20201264; in both cases, they have been financed through the Fondo Europeo de Desarrollo Regional 2014-2020 (FEDER funds). It has also been supported by the University of the Basque Country within the scholarship for training of research staff with code PIF20/135

A Fixed-Latency Architecture to Secure GOOSE and Sampled Value Messages in Substation Systems

International Electrotechnical Commission (IEC) 62351-6 standard specifies the security mechanisms to protect real-time communications based on IEC 61850. Generic Object Oriented Substation Events (GOOSE) and Sampled Value (SV) messages must be generated, transmitted and processed in less than 3 ms, which challenges the introduction of IEC 62351-6. After evaluating the security threats to IEC 61850 communications and the state of the art in GOOSE and SV security, this work presents a novel architecture based on wire-speed processing able to provide message authentication and confidentiality. This architecture has been implemented and tested to evaluate its performance, resource usage, and the latency introduced. Other proposals in the scientific literature do not support real-time traffic, so they are not suitable for GOOSE and SV messages. Whereas the others exceed the target latency of 3 ms or do not comply with the standards, our design authenticates and encrypts real-time IEC 61850 data in less than 7 mu s-predictable latency-, and complies with IEC 62351:2020.This work was supported in part by the Ministerio de Economia y Competitividad of Spain under Project TEC2017-84011-R, in part by Fondo Europeo de Desarrollo Regional (FEDER) Funds through the Doctorados Industriales program under Grant DI-15-07857, and in part by the Department of Education, Linguistic Policy and Culture of the Basque Government through the Fund for Research Groups of the Basque University System under Grant IT978-16

A Survey on IEEE 1588 Implementation for RISC-V Low-Power Embedded Devices

IEEE 1588, also known as the Precision Time Protocol (PTP), is a standard protocol for clock synchronization in distributed systems. While it is not architecture-specific, implementing IEEE 1588 on Reduced Instruction Set Computer-V (RISC-V) low-power embedded devices demands considering the system requirements and available resources. This paper explores various approaches and techniques to achieve accurate time synchronization in such instruments. The analysis covers software and hardware implementations, discussing each method’s challenges, benefits, and trade-offs. By examining the state-of-the-art in this field, this paper provides valuable insights and guidance for researchers and engineers working on time-critical applications in RISC-V-based embedded systems, aiding in selecting the most-suitable stack for their designs.This work was partially supported by the ECSEL Joint Undertaking in the H2020 project IMOCO4.E, grant agreement No.10100731, and by the Basque Government within the fund for research groups of the Basque University System IT1440-22 and KK-2023/00015

Encryption AXI Transaction Core for Enhanced FPGA Security

The current hot topic in cyber-security is not constrained to software layers. As attacks on electronic circuits have become more usual and dangerous, hardening digital System-on-Chips has become crucial. This article presents a novel electronic core to encrypt and decrypt data between two digital modules through an Advanced eXtensible Interface (AXI) connection. The core is compatible with AXI and is based on a Trivium stream cipher. Its implementation has been tested on a Zynq platform. The core prevents unauthorized data extraction by encrypting data on the fly. In addition, it takes up a small area—242 LUTs—and, as the core’s AXI to AXI path is fully combinational, it does not interfere with the system’s overall performance, with a maximum AXI clock frequency of 175 MHz.This work has been supported within the fund for research groups of the Basque university system IT1440-22 by the Department of Education and within the PILAR ZE-2020/00022 and COMMUTE ZE-2021/00931 projects by the Hazitek program, both of the Basque Government, the latter also by the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20201264 and IDI-20220543 and through the Fondo Europeo de Desarrollo Regional 2014–2020 (FEDER funds)